Package-Level Chiplet Consortium: Unifying Components for Enhanced Microchip Technology
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The Universal Chiplet Interconnect Express (UCIe) is an open standard that enables high-bandwidth, low-latency interconnects between chiplets in semiconductor packages. The UCIe Consortium, which manages this standard, includes industry heavyweights such as AMD, Intel, Qualcomm, TSMC, Google Cloud, Meta, and Microsoft, all aiming for broad adoption of this technology.
Recent developments in UCIe have been on full display, with companies like Cadence actively showcasing UCIe technology. At the TechXchange event, Cadence demonstrated how their tools and IP support the development of chiplet-based multi-die systems that leverage UCIe for interoperability and integration.
The TechXchange event also featured a presentation on designing with UCIe chiplets, offering insights into practical applications of the standard. The presentation showcased a real-world example of UCIe implementation, highlighting the technology's potential in the semiconductor industry.
A video introduction to UCIe, presented by Brian Rea, Marketing WorkGroup Chair at the UCIe Consortium, provides a short overview of the standard.
Meanwhile, other companies are pushing UCIe implementations further. For instance, Global Unichip Corp. (GUC) successfully taped out UCIe PHY Face-Up IP on TSMC’s advanced N5 process, integrating with TSMC’s SoIC-X packaging technology to deliver high bandwidth for AI, HPC, and networking. This IP achieves 36 Gbps performance and power efficiency gains, deployed within real multi-die chip packages using UCIe.
The latest standard for UCIe is UCIe 2.0, which is fully backwards compatible with previous versions. UCIe 2.0 includes the optional UCIe DFx Architecture (UDA), which supports a management fabric connecting chiplets for enhanced testing, telemetry, and debugging.
In summary, Cadence's demonstrations and GUC's tape-outs on TSMC processes are concrete examples of UCIe implementations in development and production. These examples showcase UCIe's role as a foundational open interconnect for next-generation chiplet-based semiconductors. The ecosystem continues to grow rapidly with major semiconductor and cloud companies collaborating on this open standard.
Technology and data-and-cloud-computing are integral components of the UCIe ecosystem, as companies like Google Cloud and Microsoft are part of the UCIe Consortium, working towards the broad adoption of this interconnect technology. Current developments, such as Cadence's tools and IP for chiplet-based multi-die systems and Global Unichip Corp.'s (GUC) UCIe PHY Face-Up IP on TSMC’s advanced N5 process, demonstrate its application and potential in both the semiconductor industry and data-intensive domains like AI, HPC, and networking.
