Analysis of HDI PCB Design: Collaborate with Your Partner in HDI Board Development
In the world of electronics, the design of High Density Interconnect (HDI) Printed Circuit Boards (PCBs) presents a unique set of challenges, especially when Ball Grid Arrays (BGAs) with pin pitches smaller than 0.5mm are involved. John Levreault, an analog design engineer with over 25 years of experience in mixed-signal board design, shares his insights from a recent project involving the design of an HDI PCB for a multimedia processor based on a Texas Instruments OMAP.
## The Design Challenge
The project involved several boards in a stack, with some joined by board-to-board connectors and others requiring flex connections. The OMAP was packaged in a BGA with pins on a 0.5mm pitch, while another device was packaged in a QFN. The board also carried some flash memory in a large package. The most challenging routing task was with the power management chip (TPS65950), which had 209 pins on a 0.4mm pitch.
## Routing Strategies
To navigate the dense routing requirements, John employed several strategies. Layer management was crucial to minimise costs and ensure signal integrity. Techniques like microvias and buried vias were essential for optimising space and reducing layer count. Via-in-Pad Technology was used to place vias directly under BGA pads, reducing trace lengths and improving electrical performance.
## Collaboration with Manufacturers
Early collaboration between chip, package, and PCB designers is key to manage dependencies, optimise routing, and reduce costs. John partnered with Sierra Circuits to build the board, receiving advice on how to architect it for the most efficient, manufacturable design. Early sharing of designs with manufacturers ensures they can support advanced techniques like HDI processes and microvia drilling.
## Avoiding 'Armchair Engineering'
Practical experience and continuous learning are essential to avoid relying solely on theoretical knowledge. John emphasises the importance of simulation software to validate signal integrity and thermal performance, and building prototypes to test real-world behaviour. Incorporating feedback from both simulations and prototypes refines designs and ensures they meet performance and reliability standards.
The next project involved a wearable personal communication device, consolidated in six chips. Most of the passives were 0402 capacitors, with two 0603 bulk capacitors. The use of HDI board architecture was driven by the presence of BGAs with a 0.4mm pin pitch. Texas Instruments recommends close coordination and communication between the device supplier, the PCB designer, the board fabricator, and the assembly shop for fine-pitch board design.
In the project involving a wearable personal communication device, the use of High Density Interconnect (HDI) board architecture was driven by the presence of Ball Grid Arrays (BGAs) with a 0.4mm pin pitch. This project also required the use of controlled impedance technology to navigate the dense routing requirements and ensure signal integrity.
